1. Field of the Invention
The present invention relates to a method for forming a liquid crystal display (LCD) panel, and more specifically, to a method for forming pads of a thin film transistor LCD (TFT-LCD)panel.
2. Description of the Prior Art
The TFT-LCD panel utilizes a matrix of TFTs in conjunction with other electrical elements, such as capacitors and bonding pads, as switches for driving liquid crystal pixels to produce brilliant images. Since the TFT-LCD panel has the; advantages of being lightweight, having low energy consumption, and being free of radiation emission, the TFT-LCD has been widely used in various portable products, such as notebooks, personal digital assistants (PDA), etc., and even has a great potential to replace the conventional CRT monitor.
Basically, the TFT-LCD panel includes a top substrate, a bottom substrate, and liquid crystal materials filled between the top substrate and the bottom substrate. Specifically, the bottom substrate includes a plurality of scan lines, a plurality of signal lines perpendicular to the scan lines, and a plurality of bonding pads electrically connected to corresponding driving integrated circuits (ICs) positioned on the bottom substrate. Furthermore, at least one TFT is positioned at an intersection of each scan line and each signal line, and used as a switch device of a pixel of the LCD panel.
Please refer to FIG. 1 to FIG. 7, which are schematic diagrams illustrating a method for forming a conventional LCD panel 10. FIG. 6 is a cross-sectional view along line I—I of the LCD panel 10 shown in FIG. 5. FIG. 7 is a cross-sectional view along line II—II of the LCD panel 10 shown in FIG. 5. As shown in FIG. 1, a glass substrate 12 with a pixel array area 14, a gate pad area 16, and a source pad area 18 positioned on the glass substrate 12 for forming a plurality of pixels 48, a plurality of gate pads 50, and a plurality of source pads 52 (as shown in FIG. 5) are provided.
As shown in FIG. 2, a first metal layer (not shown in FIG. 2) is deposited on the glass substrate 12, and a first photo-etching-process (PEP) is performed on the first metal layer to form a plurality of parallel scan lines 20 and a plurality of gate electrodes 22 inside the pixel array area 14, a shorting bar 24 inside the gate pad area 16, and a comb-shaped shorting bar 26 inside the source pad area 18 simultaneously. The scan lines 20 extend into the gate pad area 16 and are electrically connected to the shorting bar 24. Specifically, portions of the scan lines 20 positioned inside the gate pad area 16 are used as pad electrodes 28 of the gate pads, and portions of the comb-shaped shorting bar 26 positioned inside the source pad area 18 are used as pad electrodes 38 of the source pads. Typically, the shorting bars 24 and 26 are used to perform a subsequent electrical testing process for checking the scan lines 20 and the signal lines formed later (not shown in FIG. 2). After that, an insulating layer 25 (as shown in FIGS. 6–7) and a doped amorphous silicon layer (not shown in FIG. 2) are sequentially formed on the glass substrate 12, and a second PEP is performed on the doped amorphous silicon layer to form a plurality of active layers 30 covering corresponding gate electrodes 22 inside the pixel array area 14, and remove portions of the doped amorphous silicon layer and the insulating layer 25 outside the pixel array area 14 simultaneously.
Then as shown in FIG. 3, a second metal layer (not shown in FIG. 3) is deposited on the glass substrate 12 after performing the second PEP. Further, a third PEP is performed on the second metal layer to form a plurality of signal lines 32 perpendicular to the scan lines 20, a plurality of source electrodes 34, and a plurality of drain electrodes 36 inside the pixel array area 14. Moreover, each signal line 32 is partially overlapped with an underlying pad electrode 38.
As shown in FIG. 4, a passivation layer 39 (as shown in FIGS. 6–7) is formed on the glass substrate 12. Further, a fourth PEP is performed on the passivation layer 39 to form at least one via hole 40 at each drain electrode 36 of the pixel array area 14, at least one contact hole 42 at an overlapped area of each scan line 32 and each pad electrode 38, and simultaneously remove portions of the passivation layer 39 outside the pixel array area 14. Afterwards, a transparent conductive layer (not shown in FIG. 4), comprising indium tin oxide (ITO), is deposited on the glass substrate 12 to fill the via holes 40 inside the pixel array area 14 and the contact holes 42 inside the source pad area 18. Then, a fifth PEP is performed on the transparent conductive layer to form a patterned transparent conductive layer 44 in each pixel, a plurality of patterned transparent conductive layers 45 above the pad electrodes 28 inside the gate pad area 16, and simultaneously form a plurality of patterned transparent conductive layers 46 above the scan lines 32 and the source pad electrodes 38 inside the source pad area 18. Therefore, each signal line 32 can be electrically connected to the shorting bar 26 due to the patterned transparent conductive layers 46. Thereafter, an electrical testing process, such as a probe method is performed on each scan line 20 and each signal line 32 to ensure the quality and the illumination of the LCD panel 10. First, the probe method utilizes two electrified probes to measure the voltages of two scan lines 20. Then, the measured voltages are divided by an electric current and multiplied by a correcting factor to obtain the sheet resistance of each scan line 20. If the sheet resistance of a certain scan line 20 is much greater than that of other scan lines 20, that probably means the scan line 20 is broken. In addition, the signal lines 32 can be checked by utilizing the probe method as well to ensure the quality of the signal lines 32. As if the broken line problem of the scan lines 20 and the signal lines 32 is too serious, the LCD panel 10 is not usable and has to be abandoned.
Finally, if the LCD panel 10 is perfect after performing the electrical testing process, a subsequent process can be performed as follows. As shown in FIG. 5, the shorting bars 24 and 26 inside the gate pad area 16 and the source pad area 18 are cut by utilizing a laser method or other methods to divide the scan lines 20 and the signal lines 32 from each other, and the method for forming the conventional LCD panel 10 is completed.
The conventional method utilizes five PEPs to form the pixels 48, the gate pads 50,and the source pads 52 both with double-layer structure of the LCD panel 10. However, the source pad electrodes 38 of the conventional LCD panel 10 have utilized the patterned transparent conductive layers 46 to electrically connect the corresponding signal lines 32, as shown in FIG. 7. Therefore, the electrical testing process has to be performed after forming the patterned transparent conductive layers 46, i.e. completing the method for forming the conventional LCD panel 10. But if too many scan lines 20 and signal lines 32 are found to be broken after checking, the LCD panel 10 can not be used, which wastes manpower and material resources, so as to increase the process steps and the production cost. Consequently, in the field of LCD panels, it is a very important issue to check the broken line problem of the scan lines and the signal lines as soon as possible.